QPU Integration Engineer (Assembly & Characterization focused) (f/m/d) in Hamburg, Deutschland

eleQtron develops and operates full-stack quantum computers based on trapped-ion technology. Quantum computing is a new computing paradigm rapidly approaching commercial viability. Our unique approach combines laser-cooled trapped ions with microwave control and tailored magnetic fields. Our next-generation computing machines under development will be able to find solutions to problems that are out of reach today, thus enabling new innovative products and services for a brighter future.

Responsibilities:

• Serve as the Subject Matter Expert (SME) for advanced chip assembly and back-end packaging processes (e.g., precision dicing, flip-chip bonding, wire bonding, 3D interconnects, substrate integration, and cryogenic packaging stacks).

• Develop and optimize robust, high-yield packaging flows for fragile, high-value quantum hardware while minimizing mechanical, thermal, and electrostatic stress.

• Define, standardize, and execute multi-scale characterization protocols across wafer-level, die-level, and post-packaging stages (e.g., physical inspection, electrical probing, optical/metrology mapping, and cryogenic pre-screening).

• Feed metrology data, yield metrics, and structural/electrical defect density mapping back into process and design iterations.

• Collaborate closely with QPU designers, thermal/RF modeling engineers, and fab specialists to establish design-for-assembly (DFA) and design-for-testability (DFT) guidelines.

• Translate chip architectures into actionable assembly tolerance stacks, wire-bonding maps, and pinout/interconnect specs

• Take the lead in managing daily internal cleanroom assembly and test workflows, scheduling runs, setting baseline packaging procedures, and resolving real-time hardware deviations

• Oversee internal R&D projects to qualify novel packaging materials, interconnect schemes, and non-destructive inspection/testing techniques.

• Drive project management and technology transfer with external commercial packaging foundries, assembly OSATs, and research partners.

• Manage out-of-house assembly lines, wafer-to-wire-bond delivery schedules, yield matching, and subcontractor deliverables.

• Lead Root Cause Analysis (RCA) and Failure Mode and Effects Analysis (FMEA) for packaging failures, bond wire degradation, thermal mismatch issues, or low yield during characterization.

• Maintain Statistical Process Control (SPC) for critical dimensional tolerances, bond strengths, and physical defect counts across internal and external lots.

• Mentor test engineers, assembly technicians, and junior staff on advanced micro-assembly, ESD handling, cleanroom protocols, and automated data collection.

• Author comprehensive assembly documentation, SOPs, packaging roadmaps, and technical summary reports for executive and cross-functional teams.

Required Skills:

• Master’s or Ph.D. in Microelectronics, Electrical Engineering, Materials Science, Mechanical Engineering, Applied Physics, Nanotechnology, or a related field.

• 5+ years (or equivalent extensive industry experience) of hands-on experience in microelectronics assembly, advanced semiconductor packaging, or chip characterization within a cleanroom environment (Class 10 / 100 / ISO 4–5).

• Deep technical expertise in post-fab assembly techniques (e.g., flip-chip bonding, thermocompression/ultrasonic wire bonding, precision die attach, substrates/interposers, and encapsulation).

• Extensive experience in executing structural, optical, and electrical characterization protocols (e.g., automated wafer probing, SEM, optical profilometry, shear/pull testing, and defect mapping).

• Demonstrated track record of managing joint development projects (JDPs) or technology transfers with external packaging foundries, OSATs, or characterization labs.

• Strong project management capabilities, including timeline management, risk mitigation, and tracking vendor deliverables.

• Solid understanding of Statistical Process Control (SPC), Design of Experiments (DOE), PFMEA, and structured RCA techniques (e.g., 8D, 5-Whys, Fishbone).

• Proficiency in scripting and data processing tools (e.g., Python using Pandas/NumPy, MATLAB, or SQL) for multi-chip yield extraction, automated analysis, and visual dashboarding.

• Strong leadership capabilities with a track record of bridging communication gaps between multi-disciplinary design, fab, assembly, and testing teams.

• Fluent in English (written and spoken) with excellent technical writing and presentation skills.
  

We value (Bonus): 

• Experience in quantum hardware packaging (e.g., low-loss superconducting interconnects, 3D integration/TSVs, or high-density cryogenic wiring/PCB interfaces).

• Hands-on experience with automated wafer probers, high-throughput inspection tools, or cryogenic characterization setups.

• Proven experience establishing assembly inspection lines or setting up cleanroom packaging tools from scratch.

• Background in managing external vendor contracts, assembly IP, and wafer-to-module.

• Competitive salary: We value our team members and therefore provide remunerations that reflect this, additionally rewarding achievements.

• Flexible working hours : We offer personal freedom through a variety of flexible work schedules

• Team spirit: In our international and diverse team, and with our regular team events, having fun at work is simply part of the culture

• Further development: We want to grow together and so we offer our team members needs-based, individualized further training as well as plenty of room for personal development

• Wellness Package : We offer health-promoting benefits such as fitness programs like UrbanSportsClub to support your well-being

• Bike Leasing: Stay Mobile and Sustainable with Our Company Bike Leasing Program

• Moving Benefits: A warm welcome! We are happy to support employees who move for us with a bonus

• At the forefront : Work at the forefront of technology, where academic research meets commercial applications 

• Modern workplace: We have a high-quality infrastructure with laboratory space, offices and meeting rooms