Work in a cross-functional team that delivers high quality on-chip IPs immune to ESD/EOS and latchup events. Ensure ESD robust designs with minimum cost to mission-mode functions.

Responsibilities

Define the ESD methodology for all silicon developed by Apple and to specify the chip and IP level ESD requirements.
Design ESD protection devices and circuits to meet design requirements -Develop test structures to characterize Si for ESD/LUP properties.
Develop design rules based on Si characterization data.
Collaborate with foundry on ESD library and ESD/LUP rule development activities.
Maintain an ESD device library to support internal and external design teams.
Generate or review ESD/LUP testing plans for Apple and vendor ICs.
Manage the sign-off reviews with internal design teams, external vendors and foundries.
Drive ESD/LUP related debug activities.

Minimum Qualifications

BS and 10+ years of relevant industry experience.
Proficiency in English language is required.

Preferred Qualifications

MS and 8+ years relevant industry experience.
Deep understanding of transistor device characteristics.
Solid understanding of models used for testing ESD, including HBM, CDM, MM and IEC-61000-4-2.
Knowledge of state-of-the-art ESD circuit design techniques and topologies.
Hands-on experience with design/layout EDA tools, including Virtuoso, Calibre, Allegro, etc.
Knowledge of ESD checking tools like PERC and Pathfinder.
Experience with Si processes used for high voltage, RF, or advanced ASICs.
Experience with ESD/LUP test and characterization equipment.
Strong initiative, collaboration, and ownership of responsibilities, productive, able to meet challenging deadlines.
Excellent written and verbal communication skills.

Experienced ESD Engineer

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